High density non-volatile memory arrays are used to store digital data for computer systems and other electronic devices. In such memory arrays, reference lines are used in addition to bit-lines and word lines to store digital data through selection transistors of the array and to access the data during read operations. Active/diffusion is typically used to connect the selection transistors to such reference lines. For example, FIG. 1 is a schematic illustration of a classical read-only memory (ROM) cell 10, including a reference line 12 to ground.
With dimensions of transistors continually decreasing in new products and devices, the resistance of such active/diffusion reference lines is increasing significantly. A resulting undesired voltage drop between the reference line and the selection transistor is therefore also increasing, and the operation margins in which a correct read operation can be performed are drastically reduced. Also, supply voltages are decreasing, further reducing the read margins of the memory array. This makes the reading scheme in memory arrays more critical, since there is a greater risk of read failures.
Current designs deal with these potential read operation problems in various ways. A ROM cell typically uses an NMOS or PMOS transistor. As shown in the schematic illustration of a memory cell transistor 14 of FIG. 2, each memory cell transistor has a word line (row) 16, a bit-line (column) 18, and a reference line (rl) 20. The word line 16 connects all the gates of all the transistors on the same row of the array. The bit-line 18 connects all the drains (or the sources) of all the transistors on the same column of the array. The reference line 20 is common to several cells and is connected to the source (or the drain) of each transistor.
Table 1 provides an example of content of a memory having 5 word lines (Li−2, . . . , Li+2) and 5 bit-lines (Bj−2, . . . , Bj+2). This memory content is used as an example for all the memory array embodiments described herein.
TABLE 1Content of the cellBj − 2Bj − 1BjBj + 1Bj + 2Li + 201101Li + 101001Li10100Li − 100110Li − 210111
A reference line can be implemented either horizontally or vertically relative to the rows and columns of the memory array. FIG. 3 is a schematic illustration of a ROM array 30 having horizontal reference lines 32 parallel to horizontal word lines 33. In the memory array example 30, each horizontal word line 33 and vertical bit-line 36 intersect at a memory cell transistor 34, where disconnected inactive transistors provide a “1” value, and active transistors having connected source and drain terminals provide a “0” value. Each two adjacent cells 34 share the same reference line 32. Thus, one extra line is required for use as the reference line, for every two rows of transistors. A bit-line 36 is connected to the source (or the drain) of a cell transistor if the content is “0”, or the bit-line 36 is not connected to the cell transistor if the content of the cell is “1.”
In the embodiment of FIG. 3, the reference lines 32 can be implemented as active/diffusion lines or as metal lines. When using active/diffusion reference lines, additional columns are regularly inserted in the array to connect an active/diffusion reference line to a vertical metal reference line in order to reduce the active/diffusion resistance in the line. This solution, however, increases the area of the memory array. Metal reference lines can alternatively be used, which reduce the voltage drop across the reference lines, but still increase the area of the cell due to the more restrictive design rules required by metal lines.
Vertical metal reference lines can be used generally in two different designs. FIG. 4 is a schematic diagram of one example of a prior art classical design, an array 40 having vertical bit-lines 44 and reference lines 42. Each cell transistor of one word line i shares its drain (and/or source) with the cell transistor on the next adjacent word line i+1 and/or i−1. To program a “0” in the array, the source and drain of a cell are connected between the target bit-line 44 to be read and an adjacent reference line 42. To program a “1” in the array, the source and drain of the cell are connected together on the target bit-line 44 to be read or to an adjacent reference line 42, depending on the last programmed cell (i.e., the line 42 or 44 connected to is the same line to which the tied source or drain of the last adjacent programmed cell is connected). This design reduces the voltage drop of the reference lines 42 but considerably increases the area of the cell, as there is one additional reference line 42 for each bit-line 44.
A second design of a memory array having vertical reference lines can also be used. One example of the second design is described in U.S. Pat. No. 5,917,224, and is illustrated in the schematic diagram of FIG. 5 as array 60. Each reference line 62 is shared between two different bit-lines 64. As in the classical design, each cell transistor of one word line i shares its drain (and/or source) with the cell transistor on the next adjacent word line i+1 and/or i−1. To program a “0” in the array, the source and drain of a cell are connected between the target bit-line 64 to be read and an adjacent reference line 62. To program a “1” in the array, the source and drain of the cell are connected together on the target bit-line 64 to be read or to an adjacent reference line 62, depending on the last adjacent programmed cell. This approach reduces the voltage drop of the reference lines, but increases the area of the cell, as there is still n/2 more reference lines 62 for each n bit-lines.
Accordingly, a high-density non-volatile memory array allowing more robust reading operations than existing designs while having the same or reduced physical area would be desirable in many applications.